Advances in microprocessor technology have been important engines for growth in the computing industry for decades. This continued growth is now challenged by significant roadblocks that include increasingly unreliable technology, strict limits on power consumption and the difficulties in developing reliable parallel software for chip multiprocessors. We focus on designing architectures that address these challenges on multiple fronts.
Variation-Aware Microprocessor Design
Manufacturing process challenges have caused variation in transistor characteristics such as switching speed and power consumption. Process variation together with temperature and voltage variations (generally referred to as parameter variations) are having an increasingly detrimental effect on current and future generations of microprocessors, resulting in lower chip frequency, higher power consumption and decreased reliability.
We investigate architectures that incorporate variation-awareness in the design process as well as in runtime adaptation and optimization solutions designed to achieve better reliability and energy efficiency in increasingly unpredictable systems.
Ultra-low Power Multicore Architectures
Power management in chip multiprocessors continues to be one of the primary concerns for chip designers. With future multicores expected to have dozens or even hundreds of cores on a single die power demands will far exceed what is safe to deliver to the chip and practical to dissipate with standard cooling methods. Drastic solutions are needed to ensure future microprocessors will not hit a power wall that will prevent them from taking full advantage of technology scaling.
Our lab is developing solutions for enabling ultra-low voltage operation of multicore chips in an effort to dramatically improve energy efficiency of computation.
Architectural Solutions for Software Reliability
Software is growing in complexity and becoming increasingly prone to design and implementation errors. Given the current wide-spread adoption of chip multiprocessors, this problem is only getting worse. Parallel applications are especially hard to write and debug, being prone to nondeterministic synchronization bugs such as data races.
In this project we investigate architectural solutions for making the software more robust by providing software-controlled hardware primitives that enable efficient runtime monitoring and debugging solutions.